1. Field of the Invention
The present invention relates generally to data transmission. More particularly, the present invention relates to amplifier/buffer bandwidth extension for high-speed tranceivers.
2. Background Art
There is a continuous push in the art to provide higher bandwidth data links for fast and large volume data transfer. With the increased proliferation of digital data including images, video, and other data, the need to quickly transfer digital data from one location to another becomes increasingly important. For example, high-speed data links are necessary to send video signals to a display, to transfer data across networks, to archive data to disks, and to perform other tasks.
For high-speed tranceivers with data rates exceeding 45 Gbs/s, quarter rate architecture is often used to relax the speed constraints for critical decision circuits such as samplers and slicers. However, this architecture poses some implementation challenges. Specifically, to acquire four data bits and four edge bits to create an optimal sampling point for the clock data recovery (CDR), eight parallel samplers and slicers are needed. This heavy load poses difficulties in amplifier/buffer design, as conventional bandwidth extension techniques cannot provide sufficient gain and bandwidth boosting to meet the amplitude and jitter specifications required by the samplers and slicers.
Accordingly, there is a need to overcome the drawbacks and deficiencies in the art by providing an amplifier design suitable for high-speed transceivers with increasing data rate and heavier load.